HW/SW partitioning of an embedded instruction memory decompressor

S. Weiss; S. Beren

doi:10.1145/371636.371668

HW/SW partitioning of an embedded instruction memory decompressor

S. Weiss^*, S. Beren

^*Corresponding author for this work

School of Electrical Engineering

Tel Aviv University

Research output: Contribution to conference › Paper › peer-review

Abstract

We introduce a new PLA-based decoder architecture for random-access run-time decompression of compressed instruction memory in embedded systems. The compression method employs class-based coding. We show that this new decoder architecture can be extended to provide high throughput decompression. The design of the decompressor is based on the following HW/SW tradeoff: decoding is done in hardware to provide high throughput, yet the codebook used for decompression is fully programmable.

Original language	English
Pages	36-41
Number of pages	6
DOIs	https://doi.org/10.1145/371636.371668
State	Published - 2001
Event	9th International Symposium on Hardware/Software Codesign - Copenhagen, Denmark Duration: 25 Apr 2001 → 27 Apr 2001

Conference

Conference	9th International Symposium on Hardware/Software Codesign
Country/Territory	Denmark
City	Copenhagen
Period	25/04/01 → 27/04/01

Keywords

Compressed instruction memory
Embedded systems

Access to Document

10.1145/371636.371668

Cite this

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abstract = "We introduce a new PLA-based decoder architecture for random-access run-time decompression of compressed instruction memory in embedded systems. The compression method employs class-based coding. We show that this new decoder architecture can be extended to provide high throughput decompression. The design of the decompressor is based on the following HW/SW tradeoff: decoding is done in hardware to provide high throughput, yet the codebook used for decompression is fully programmable.",

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HW/SW partitioning of an embedded instruction memory decompressor

Abstract

Conference

Keywords

Access to Document

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