Abstract
We present an algorithm for IEEE floating-point addition. The latency of the addition algorithm for double precision is roughly 24 logic levels, not including delays of latches between pipeline stages. The algorithm accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly rounded sum/difference in the format required by the IEEE Standard. The presentation of the algorithm is technology independent and can serve as basis for evaluation and comparison with other floating-point addition algorithms.
| Original language | English |
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| Pages | 142-149 |
| Number of pages | 8 |
| State | Published - 1998 |
| Externally published | Yes |
| Event | Proceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA Duration: 5 Oct 1998 → 7 Oct 1998 |
Conference
| Conference | Proceedings of the 1998 IEEE International Conference on Computer Design |
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| City | Austin, TX, USA |
| Period | 5/10/98 → 7/10/98 |