How many logic levels does floating-point addition require?

Peter M. Seidel, Guy Even

Research output: Contribution to conferencePaperpeer-review

Abstract

We present an algorithm for IEEE floating-point addition. The latency of the addition algorithm for double precision is roughly 24 logic levels, not including delays of latches between pipeline stages. The algorithm accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly rounded sum/difference in the format required by the IEEE Standard. The presentation of the algorithm is technology independent and can serve as basis for evaluation and comparison with other floating-point addition algorithms.

Original languageEnglish
Pages142-149
Number of pages8
StatePublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA
Duration: 5 Oct 19987 Oct 1998

Conference

ConferenceProceedings of the 1998 IEEE International Conference on Computer Design
CityAustin, TX, USA
Period5/10/987/10/98

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