Hasty design, futile patching and the elaboration of rigor

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Abstract

"Two wrongs don't make a right." In the last two years, we observed repeated hasty designs, followed by futile patching of programming solutions, which yielded (and re-yielded) erroneous outcomes. In this paper, we illuminate and illustrate diverse characteristics of these undesired design and patching phenomena, and offer a didactic approach of using them for elaborating students' awareness of rigor. We advocate such an elaboration in textbooks and teaching materials, as one may learn and benefit from the wrong way no less than the right one.

Original languageEnglish
Title of host publicationITiCSE 2007
Subtitle of host publication12th Annual Conference on Innovation and Technology in Computer Science Education - Inclusive Education in Computer Science
PublisherAssociation for Computing Machinery
Pages161-165
Number of pages5
ISBN (Print)1595936106, 9781595936103
DOIs
StatePublished - 2007
EventITiCSE 2007: 12th Annual Conference on Innovation and Technology in Computer Science Education - Inclusive Education in Computer Science - Dundee, Scotland, United Kingdom
Duration: 25 Jun 200727 Jun 2007

Publication series

NameITiCSE 2007: 12th Annual Conference on Innovation and Technology in Computer Science Education - Inclusive Education in Computer Science

Conference

ConferenceITiCSE 2007: 12th Annual Conference on Innovation and Technology in Computer Science Education - Inclusive Education in Computer Science
Country/TerritoryUnited Kingdom
CityDundee, Scotland
Period25/06/0727/06/07

Keywords

  • Patching
  • Programming errors
  • Rigor

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