Extending endurance of NROM memories to over 10 million program/erase cycles

Yakov Roizin*, Evgeny Pikhay, Michael Lisiansky, Alexey Heiman, Eli Alon, Efraim Aloni, Amos Fenigstein

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

We report on NROM (nitride read only) memory with enhanced endurance/retention. A novel "refresh" is introduced into the cycling algorithm to exclude parasitic electron trapping in the memory transistor. Negative gate pulses are applied when the drain voltage in the erase procedure reaches the threshold value. The memory stack is optimized to allow injection of holes from the substrate through the bottom oxide (BOX). More than 10 million program/erase (P/E) cycles with excellent retention are easily achieved.

Original languageEnglish
Title of host publication21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006
Pages74-75
Number of pages2
DOIs
StatePublished - 2006
Externally publishedYes
Event21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006 - Monteray, CA, United States
Duration: 12 Feb 200616 Feb 2006

Publication series

Name21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006
Volume2006

Conference

Conference21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006
Country/TerritoryUnited States
CityMonteray, CA
Period12/02/0616/02/06

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