Embedded instruction memory in automotive engine controllers

Tal Oved, Shlomo Weiss

Research output: Contribution to journalArticlepeer-review

Abstract

Embedded systems currently account for all but 2% of the microprocessor market. Yet often embedded processor cores are simply streamlined versions of microprocessors that were designed for desktop computers. In computer architecture research, the Standard Performance Evaluation Corporation (SPEC) benchmark programs are often used to evaluate the performance of computer systems. The characteristics of the SPEC programs do not match typical embedded applications, however, and therefore it is not clear to what extent performance studies conducted using the SPEC benchmarks are applicable to embedded systems. In this paper, we focus on a specific segment of the embedded market: automotive engine controllers. Using data gathered by tracing a state-of-the-art automotive controller, we present simulation results for a memory system that consists of a main memory containing compressed programs, a bus used to fetch compressed instruction blocks, a decompression subsystem, and an uncompressed instruction cache. We look at a number of system parameters, including the bus load, the average memory access time, and the performance ratio of the compressed versus uncompressed system. We also present an analysis of the static and dynamic (run-time) system behavior.

Original languageEnglish
Pages (from-to)173-183
Number of pages11
JournalIEEE Transactions on Vehicular Technology
Volume52
Issue number1
DOIs
StatePublished - Jan 2003

Keywords

  • Automotive
  • Code compression
  • Embedded processors
  • Engine control
  • Memory systems

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