TY - JOUR
T1 - Electrical and material properties of MOS capacitors with electrolessly deposited integrated copper gate
AU - Shacham-Diamand, Yosi
AU - Israel, Barak
AU - Sverdlov, Yelena
N1 - Funding Information:
The work was partially supported by grant #8460-1-98 from the Israeli ministry of science. Thanks to Mark Oksman from Tel-Aviv University and Dr. Roi Shaviv from Tower semiconductors Ltd. for their support in samples preparation.
PY - 2001/3
Y1 - 2001/3
N2 - The electrical properties of electroless-deposited barriers were studied using metal-oxide-silicon (MOS) capacitors with thin (14 nm) thermal oxide. Three different metal electrodes were deposited on a thin sputtered Co seed layer: (a) sputtered Al, (b) electroless Co(W,P) and (c) electroless multilayer of Co(W,P)/Cu/Co(W,P). The study includes thermal stress in vacuum in the 300-600 °C temperature range, for periods of 30 min to 4 h, followed by electrical characterization. The high-frequency capacitance versus voltage (C-V) characteristics of the capacitors was near ideal after annealing at 300-500 °C for 30 min. After annealing at higher temperatures for longer times the inversion capacitance increased above the ideal high-frequency value while the flat band voltage remained unchanged. The minority carrier lifetime, as obtained from transient capacitance analysis, was in the range of 60 μs for samples annealed at temperatures below 500 °C. It dropped for the samples with copper layers to 12 μs after 520 °C anneal for 2 h and to 1 μs after 600 °C for 4 h while remaining in the range of 50-60 μs for the samples with either electroless barrier or aluminum. AES profiling indicated that the copper profile remained unchanged after annealing at temperatures up to 500 °C anneal for 30 min. Above 520 °C, the copper profile showed significant diffusion onto the Co(W,P) barrier layer underneath and much less diffusion onto the Co(W,P) capping layer above.
AB - The electrical properties of electroless-deposited barriers were studied using metal-oxide-silicon (MOS) capacitors with thin (14 nm) thermal oxide. Three different metal electrodes were deposited on a thin sputtered Co seed layer: (a) sputtered Al, (b) electroless Co(W,P) and (c) electroless multilayer of Co(W,P)/Cu/Co(W,P). The study includes thermal stress in vacuum in the 300-600 °C temperature range, for periods of 30 min to 4 h, followed by electrical characterization. The high-frequency capacitance versus voltage (C-V) characteristics of the capacitors was near ideal after annealing at 300-500 °C for 30 min. After annealing at higher temperatures for longer times the inversion capacitance increased above the ideal high-frequency value while the flat band voltage remained unchanged. The minority carrier lifetime, as obtained from transient capacitance analysis, was in the range of 60 μs for samples annealed at temperatures below 500 °C. It dropped for the samples with copper layers to 12 μs after 520 °C anneal for 2 h and to 1 μs after 600 °C for 4 h while remaining in the range of 50-60 μs for the samples with either electroless barrier or aluminum. AES profiling indicated that the copper profile remained unchanged after annealing at temperatures up to 500 °C anneal for 30 min. Above 520 °C, the copper profile showed significant diffusion onto the Co(W,P) barrier layer underneath and much less diffusion onto the Co(W,P) capping layer above.
UR - http://www.scopus.com/inward/record.url?scp=0034825608&partnerID=8YFLogxK
U2 - 10.1016/S0167-9317(00)00462-7
DO - 10.1016/S0167-9317(00)00462-7
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AN - SCOPUS:0034825608
SN - 0167-9317
VL - 55
SP - 313
EP - 322
JO - Microelectronic Engineering
JF - Microelectronic Engineering
IS - 1-4
ER -