EEPROM memory stack with scaled down thickness

Ruth Shima Edelstein; Chris Cork; Efraim Aloni; Nachi Vofsy; Yakov Roizin

doi:10.1016/j.mee.2004.01.038

EEPROM memory stack with scaled down thickness

Ruth Shima Edelstein, Chris Cork, Efraim Aloni, Nachi Vofsy, Yakov Roizin^*

^*Corresponding author for this work

Tower Semiconductors Ltd.

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

We studied OAO (oxide-α-Si-oxide) memory stacks of 450-600 Å total thickness that were part of multi-bit EEPROM elements. Information was stored in two isolated Poly/ralpha-Si floating gates located above the channel edges. The floating gate was 250-400 Å LPCVD amorphous Si or Poly, surrounded by 70 Å bottom oxide and 125 Å top oxide. Reliability of the new memory stack was evaluated, and the breakdown voltage (V_bd) and charge (Q_bd) of the optimized stack are high enough to use in advanced embedded EEPROM memories, and in particular in memory cells with two isolated poly floating gates.

Original language	English
Pages (from-to)	421-425
Number of pages	5
Journal	Microelectronic Engineering
Volume	72
Issue number	1-4
DOIs	https://doi.org/10.1016/j.mee.2004.01.038
State	Published - Apr 2004
Externally published	Yes
Event	Proceedings of the 13th Biennial Conference on Insulating Film - Barcelona, Spain Duration: 18 Jun 2003 → 20 Jun 2003

Funding

Funders	Funder number
Israeli Ministry of Industry and Trade, Consortium of Emerging Dielectrics and Conductor Technologies

Keywords

Amorphous Si
Breakdown
EEPROM
Multi-bit memory cell
Scaling

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1016/j.mee.2004.01.038

Cite this

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title = "EEPROM memory stack with scaled down thickness",

abstract = "We studied OAO (oxide-α-Si-oxide) memory stacks of 450-600 {\AA} total thickness that were part of multi-bit EEPROM elements. Information was stored in two isolated Poly/ralpha-Si floating gates located above the channel edges. The floating gate was 250-400 {\AA} LPCVD amorphous Si or Poly, surrounded by 70 {\AA} bottom oxide and 125 {\AA} top oxide. Reliability of the new memory stack was evaluated, and the breakdown voltage (Vbd) and charge (Qbd) of the optimized stack are high enough to use in advanced embedded EEPROM memories, and in particular in memory cells with two isolated poly floating gates.",

keywords = "Amorphous Si, Breakdown, EEPROM, Multi-bit memory cell, Scaling",

author = "Edelstein, {Ruth Shima} and Chris Cork and Efraim Aloni and Nachi Vofsy and Yakov Roizin",

note = "Funding Information: This work was partially supported by the MAGNET program of the Chief Scientist Office at the Israeli Ministry of Industry and Trade, Consortium of Emerging Dielectrics and Conductor Technologies. The authors would like to thank Anatoly Sergienko and Yakov Feldman for process support.; Proceedings of the 13th Biennial Conference on Insulating Film ; Conference date: 18-06-2003 Through 20-06-2003",

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AU - Edelstein, Ruth Shima

AU - Cork, Chris

AU - Aloni, Efraim

AU - Vofsy, Nachi

AU - Roizin, Yakov

N1 - Funding Information: This work was partially supported by the MAGNET program of the Chief Scientist Office at the Israeli Ministry of Industry and Trade, Consortium of Emerging Dielectrics and Conductor Technologies. The authors would like to thank Anatoly Sergienko and Yakov Feldman for process support.

PY - 2004/4

Y1 - 2004/4

N2 - We studied OAO (oxide-α-Si-oxide) memory stacks of 450-600 Å total thickness that were part of multi-bit EEPROM elements. Information was stored in two isolated Poly/ralpha-Si floating gates located above the channel edges. The floating gate was 250-400 Å LPCVD amorphous Si or Poly, surrounded by 70 Å bottom oxide and 125 Å top oxide. Reliability of the new memory stack was evaluated, and the breakdown voltage (Vbd) and charge (Qbd) of the optimized stack are high enough to use in advanced embedded EEPROM memories, and in particular in memory cells with two isolated poly floating gates.

AB - We studied OAO (oxide-α-Si-oxide) memory stacks of 450-600 Å total thickness that were part of multi-bit EEPROM elements. Information was stored in two isolated Poly/ralpha-Si floating gates located above the channel edges. The floating gate was 250-400 Å LPCVD amorphous Si or Poly, surrounded by 70 Å bottom oxide and 125 Å top oxide. Reliability of the new memory stack was evaluated, and the breakdown voltage (Vbd) and charge (Qbd) of the optimized stack are high enough to use in advanced embedded EEPROM memories, and in particular in memory cells with two isolated poly floating gates.

KW - Amorphous Si

KW - Breakdown

KW - EEPROM

KW - Multi-bit memory cell

KW - Scaling

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T2 - Proceedings of the 13th Biennial Conference on Insulating Film

Y2 - 18 June 2003 through 20 June 2003

ER -

EEPROM memory stack with scaled down thickness

Abstract

Funding

Keywords

UN SDGs

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