TY - JOUR
T1 - Dual precision IEEE floating-point multiplier
AU - Even, Guy
AU - Mueller, Silvia M.
AU - Seidel, Peter Michael
N1 - Funding Information:
Peter-Michael Seidel studied Computer Science and Electrical Engineering at the University of Hagen, Germany, from which he graduated in 1996. He completed his PhD in computer science in 1999 at the chair of Prof. Wolfgang Paul at the University of the Saarland, Germany, where he was supported by a fellowship of the German National Science Foundation (DFG). Currently, he is an assistant professor in the Computer Science and Engineering Department at Southern Methodist University in Dallas, Texas. His current areas of research include: computer arithmetic, computer architecture, and the design of IEEE compliant floating-point units.
PY - 2000/9
Y1 - 2000/9
N2 - A new algorithm for computing IEEE-compliant rounding is presented, called injection-based rounding. Injection-based rounding is simple and facilitates using the same rounding circuitry for different precisions. We demonstrate the usefulness of injection-based rounding in a design of an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. The multiplier is designed to minimize hardware cost by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions. The latency of the multiplier is in single-precision two clock cycles and in double precision the latency is three clock cycles, where each pipeline stage contains roughly 15 logic levels.
AB - A new algorithm for computing IEEE-compliant rounding is presented, called injection-based rounding. Injection-based rounding is simple and facilitates using the same rounding circuitry for different precisions. We demonstrate the usefulness of injection-based rounding in a design of an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. The multiplier is designed to minimize hardware cost by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions. The latency of the multiplier is in single-precision two clock cycles and in double precision the latency is three clock cycles, where each pipeline stage contains roughly 15 logic levels.
UR - http://www.scopus.com/inward/record.url?scp=0034266126&partnerID=8YFLogxK
U2 - 10.1016/S0167-9260(00)00006-7
DO - 10.1016/S0167-9260(00)00006-7
M3 - מאמר
AN - SCOPUS:0034266126
VL - 29
SP - 167
EP - 180
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
SN - 0167-9260
IS - 2
ER -