We present an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the latency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fifteen logic levels. A single-precision multiplication can be followed immediately by another multiplication of either single or double-precision. A double-precision multiplication requires one stall cycle, namely, two cycles after issuing a double-precision multiplication, a new multiplication of either precision can be issued. Therefore, the throughput in single-precision is one multiplication per clock cycle, and the throughput in double-precision is one multiplication per two clock cycles. Hardware cost is reduced by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions.
|Number of pages||8|
|Journal||Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon|
|State||Published - 1997|
|Event||Proceedings of the 1997 2nd Annual IEEE International Conference on Innovative Systems in Silicon - Austin, TX, USA|
Duration: 8 Oct 1997 → 10 Oct 1997