TY - GEN
T1 - DNOC
T2 - 2015 15th IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2015
AU - Oxman, Gadi
AU - Weiss, Shlomo
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/4/27
Y1 - 2015/4/27
N2 - We present DNOC, a network-on-chip simulator. DNOC simulates custom network topologies with detailed router models. Both classic virtual channel (VC) based router models and deflection routing models are supported. We validate the simulation models against hardware RTL router models. DNOC can generate various statistics, such as network latency and power. We evaluate the simulator in three typical use cases. In stand-alone simulation, synthetic traffic generators are used to offer load to the network. In synchronous co-simulation, the simulator is integrated as a module within a larger system simulator with synchronization every simulated cycle. In the faster model based co-simulation mode, a latency model is built, and re-tuned periodically at longer time intervals. We demonstrate co-simulation by running applications from the Rodinia and SPLASH-2 benchmark sets on mesh variants. DNOC is also able to run on multiple x86 cores in parallel, speeding up the simulation of large networks.
AB - We present DNOC, a network-on-chip simulator. DNOC simulates custom network topologies with detailed router models. Both classic virtual channel (VC) based router models and deflection routing models are supported. We validate the simulation models against hardware RTL router models. DNOC can generate various statistics, such as network latency and power. We evaluate the simulator in three typical use cases. In stand-alone simulation, synthetic traffic generators are used to offer load to the network. In synchronous co-simulation, the simulator is integrated as a module within a larger system simulator with synchronization every simulated cycle. In the faster model based co-simulation mode, a latency model is built, and re-tuned periodically at longer time intervals. We demonstrate co-simulation by running applications from the Rodinia and SPLASH-2 benchmark sets on mesh variants. DNOC is also able to run on multiple x86 cores in parallel, speeding up the simulation of large networks.
UR - http://www.scopus.com/inward/record.url?scp=84937510086&partnerID=8YFLogxK
U2 - 10.1109/ISPASS.2015.7095805
DO - 10.1109/ISPASS.2015.7095805
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AN - SCOPUS:84937510086
T3 - ISPASS 2015 - IEEE International Symposium on Performance Analysis of Systems and Software
SP - 193
EP - 202
BT - ISPASS 2015 - IEEE International Symposium on Performance Analysis of Systems and Software
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 29 March 2015 through 31 March 2015
ER -