DNOC: An accurate and fast virtual channel and deflection routing network-on-chip simulator

Gadi Oxman, Shlomo Weiss

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

We present DNOC, a network-on-chip simulator. DNOC simulates custom network topologies with detailed router models. Both classic virtual channel (VC) based router models and deflection routing models are supported. We validate the simulation models against hardware RTL router models. DNOC can generate various statistics, such as network latency and power. We evaluate the simulator in three typical use cases. In stand-alone simulation, synthetic traffic generators are used to offer load to the network. In synchronous co-simulation, the simulator is integrated as a module within a larger system simulator with synchronization every simulated cycle. In the faster model based co-simulation mode, a latency model is built, and re-tuned periodically at longer time intervals. We demonstrate co-simulation by running applications from the Rodinia and SPLASH-2 benchmark sets on mesh variants. DNOC is also able to run on multiple x86 cores in parallel, speeding up the simulation of large networks.

Original languageEnglish
Title of host publicationISPASS 2015 - IEEE International Symposium on Performance Analysis of Systems and Software
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages193-202
Number of pages10
ISBN (Electronic)9781479919567
DOIs
StatePublished - 27 Apr 2015
Event2015 15th IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2015 - Philidelphia, United States
Duration: 29 Mar 201531 Mar 2015

Publication series

NameISPASS 2015 - IEEE International Symposium on Performance Analysis of Systems and Software

Conference

Conference2015 15th IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2015
Country/TerritoryUnited States
CityPhilidelphia
Period29/03/1531/03/15

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