Deterministic identity testing of depth-4 multilinear circuits with bounded top fan-in

We give the first subexponential time deterministic polynomial identity testing algorithm for depth-4 multilinear circuits with a small top fan-in. More accurately, our algorithm works for depth-4 multilinear circuits with a plus gate at the top (also known as ∑∏∑∏ circuits) and has a running time of exp(poly(log(n), log(s), k)) where n is the number of variables, s is the size of the circuit, and k is the fan-in of the top gate. In particular, when the circuit is of polynomial (or quasi-polynomial) size, our algorithm runs in quasi-polynomial time. Prior to this work, subexponential time deterministic algorithms were known for depth-3 circuits with small top fan-in and for very restricted versions of depth-4 circuits. The main ingredient in our proof is a new structural theorem for multilinear ∑∏∑∏(k) circuits. Roughly, this theorem shows that any nonzero multilinear ∑∏∑∏(k) circuit contains an "embedded" nonzero multilinear ∑∏∑(k) circuit. Using ideas from previous works on identity testing of sums of read-once formulas and of depth-3 multilinear circuits, we are able to exploit this structure and obtain an identity testing algorithm for multilinear ∑∏∑∏(k) circuits.