Delay-optimized implementation of IEEE floating-point addition

Peter Michael Seidel, Guy Even

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

Abstract

We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The FP-adder design achieves a low latency by combining various optimization techniques such as: A nonstandard separation into two paths, a simple rounding algorithm, unification of rounding cases for addition and subtraction, sign-magnitude computation of a difference based on one’s complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation. We present technology-independent analysis and optimization of our implementation based on the Logical Effort hardware model and we determine optimal gate sizes and optimal buffer insertion. We estimate the delay of our optimized design at 30.6 F04 delays for double precision operands (15.3 F04 delays per stage between latches). We overview other IEEE FP addition algorithms from the literature and compare these algorithms with our algorithm. We conclude that our algorithm has shorter latency (-13 percent) and cycle time (-22 percent) compared to the next fastest algorithm.

Original languageEnglish
Title of host publicationComputer Arithmetic
Subtitle of host publicationVolume III
PublisherWorld Scientific Publishing Co.
Pages75-91
Number of pages17
ISBN (Electronic)9789814651141
ISBN (Print)9789814651134
DOIs
StatePublished - 1 Jan 2015

Keywords

  • Buffer insertion
  • Delay optimization
  • Dual path algorithm
  • Floating-point addition
  • Ieee rounding
  • Logical effort
  • Optimized gate sizing

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