Decreasing error floor in LDPC codes by parity-check matrix extensions

Orner Fainzilber*, Eran Sharon, Simon Litsyn

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

High error floors in optimized irregular LDPC codes limit their usage in applications that require low error rates. We introduce new methods for lowering the error floor of LDPC codes, based on enhancing the code's parity-check matrix with additional linearly dependent and independent parity-checks. We prove NP hardness of certain optimization problems related to proposed methods and provide upper bound on the number of parity-checks that need to be added. We show that the proposed methods can lower the error floor of the code significantly, by several orders of magnitude, at negligible or no rate penalty.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Information Theory, ISIT 2009
Pages374-378
Number of pages5
DOIs
StatePublished - 2009
Event2009 IEEE International Symposium on Information Theory, ISIT 2009 - Seoul, Korea, Republic of
Duration: 28 Jun 20093 Jul 2009

Publication series

NameIEEE International Symposium on Information Theory - Proceedings
ISSN (Print)2157-8102

Conference

Conference2009 IEEE International Symposium on Information Theory, ISIT 2009
Country/TerritoryKorea, Republic of
CitySeoul
Period28/06/093/07/09

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