This letter presents a novel approach for designing a dynamic branch predictor. The proposed design, called decoupled-predictor literally decouples the prediction making from the prediction update stages of the scheme. This separation is intended to tailor each part for its particular task and to reduce unnecessary references to these parts. In this letter, we show that embedded digital signal processors (DSPs) can benefit from dynamic branch prediction while staying within strict memory limitations. This letter presents a detailed description of the predictor architecture and evaluates its performance through a set of trace driven simulations of embedded DSP applications. Finally, we address the design cost efficiency by offering memory saving optimizations.
- Branch prediction
- digital signal processors (DSPs)