Decoupled Branch Predictor for Embedded DSP

Konstantin Berestizshevsky*, Shlomo Weiss

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This letter presents a novel approach for designing a dynamic branch predictor. The proposed design, called decoupled-predictor literally decouples the prediction making from the prediction update stages of the scheme. This separation is intended to tailor each part for its particular task and to reduce unnecessary references to these parts. In this letter, we show that embedded digital signal processors (DSPs) can benefit from dynamic branch prediction while staying within strict memory limitations. This letter presents a detailed description of the predictor architecture and evaluates its performance through a set of trace driven simulations of embedded DSP applications. Finally, we address the design cost efficiency by offering memory saving optimizations.

Original languageEnglish
Article number8047953
Pages (from-to)57-60
Number of pages4
JournalIEEE Embedded Systems Letters
Volume10
Issue number3
DOIs
StatePublished - Sep 2018

Keywords

  • Branch prediction
  • digital signal processors (DSPs)

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