To address the problem of soft errors in chip multiprocessors, we propose Dynamic Dual Modular Redundancy(DDMR). DDMR uses known techniques and components to construct a novel multicore architecture that provides soft error detection and recovery. DDMR may be easily integrated with CMP architectures. DDMR replaces pairwise links connected at manufacturing with a new ring architecture that supports runtime linking of redundant cores. Requiring minimal area and power resources, the ring prevents loading the general purpose and more expensive CMP interconnect with transfers needed to coordinate redundant processing. DDMR uses signatures to reduce bandwidth requirements. Signatures are exchanged after short validation intervals, an approach that saves resources needed to buffer uncommitted data and reduces latencies in parallel programs. DDMR scales with the number of cores and may be used in large multicore architectures.