Recent interest in Cu-based metallization for ultra-large scale integrated (ULSI) devices has stimulated extensive studies on its thermal stability issues, as well as the search of novel deposition and etching processes. Cu is a candidate for global interconnection in the upper-level metallization in ULSI technology due to its low resistivity and high electromigration resistance. The electroless plating technique has proved capable of selective Cu growth in a planarized structure with minimum linewidth as small as 0.1 μm. Some of the practical aspects in the Cu patterning to produce non-planar and fully planar Cu fine lines will be presented in this paper. We are concerned with the thermal stability of Cu in structures of Cu Si, Cu/silicide, Cu/metals, Cu/polymer and Cu SiO2. We investigated the interfacial reactions in these structures by Rutherford backscattering (RBS), transmission electron microscopy (TEM) and Auger electron spectroscopy (AES). Cu reacts with Si, most metals and their silicides at relatively low temperatures. The adhesion of Cu on most dielectric substrates is poor. Oxidation of Cu occurs at very low temperature. These obstacles can be overcome by employing diffusion barriers, adhesion promotors, and passivation layers. Incorporation of alloying elements used in the formation of self-encapsulation and adhesion layers for Cu wiring is introduced. The validity of diffusion barriers has been tested in several copper-based layered structures. We also summarize recent work on electromigration, stress migration, and Cu dry etching in Cu-based metallization.