Computation for electromigration in interconnects of microelectronic devices

Amir Averbuch*, Moshe Israeli, Igor Ravve, Irad Yavneh

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Reliability and performance of microelectronic devices depend to a large extent on the resistance of interconnect lines. Voids and cracks may occur in the interconnects, causing a severe increase in the total resistance and even open circuits. In this work we analyze void motion and evolution due to surface diffusion effects and applied external voltage. The interconnects under consideration are three-dimensional (sandwich) constructs made of a very thin metal film of possibly variable thickness attached to a substrate of nonvanishing conductance. A two-dimensional level set approach was applied to study the dynamics of the moving (assumed one-dimensional) boundary of a void in the metal film. The level set formulation of an electromigration and diffusion model results in a fourth-order nonlinear (two-dimensional) time-dependent PDE. This equation was discretized by finite differences on a regular grid in space and a Runge-Kutta integration scheme in time, and solved simultaneously with a second-order static elliptic PDE describing the electric potential distribution throughout the interconnect line. The well-posed three-dimensional problem for the potential was approximated via singular perturbations, in the limit of small aspect ratio, by a two-dimensional elliptic equation with variable coefficients describing the combined local conductivity of metal and substrate (which is allowed to vary in time and space). The difference scheme for the elliptic PDE was solved by a multigrid technique at each time step. Motion of voids in both weak and strong electric fields was examined, and different initial void configurations were considered, including circles, ellipses, polygons with rounded corners, a butterfly, and long grooves. Analysis of the void behavior and its influence on the resistance gives the circuit designer a tool for choosing the proper parameters of an interconnect (width-to-length ratio, properties of the line material, conductivity of the underlayer, etc.).

Original languageEnglish
Pages (from-to)316-371
Number of pages56
JournalJournal of Computational Physics
Issue number2
StatePublished - 1 Mar 2001


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