Two prototypes of a distributed amplifier (DA) were implemented in 65 nm CMOS based on low-pass and highpass artificial transmission lines (ATL). The characteristic impedance and the propagation factor of ATLs were analyzed by combining the lines with an approximate CMOS cascode model. The simulated gain for the low-pass ATL DA has a peak of 13 dB at 7 GHz, 3dB bandwidth is 14.6 GHz (from 4.3 to 18.9 GHz). The simulated Psat and PO1dB are better than 15 dBm and 10 dBm up to 30 GHz. The measured performance degraded due to oscillations at 3 GHz, the measured gain is 12 dB at 7.7 GHz and 3-dB bandwidth is 7 GHz from 4.7 to 11.7 GHz. The designed 3-stage high-pass ATL DA has a simulated peak gain of 17.7 dB at 50 GHz and 3dB bandwidth of 26.4 GHz from 44.1 to 70.5 GHz. The simulated Psat is better than 8 dBm from 43 to 71 GHz. However, the measured performance was degraded because of a highly sensitive design to the passive elements modeling which was limited up to 20 GHz. The measured peak power gain is 10.1 dB at 61.5 GHz and 3-dB bandwidth is 10.3 GHz from 54.7 to 65 GHz. Peak Psat reduced to 6.8 dBm at 62 GHz.