Characterization of silane based ultra-thin barrier deposited at elevated temperature

In this work, we describe a quick turn-around characterization approach of ultra-thin layers on low dielectric constant (Low-K) interlevel dielectric using Electrochemical Impedance Spectroscopy (EIS). It is demonstrated on an organo-silane based ultra-thin Cu barrier layer, deposited from liquid phase at elevated temperatures, 90 °C - 150 °C, using high flash temperature solvents: N-methyl-2-pyrrolydone (NMP, T_flash-point = 91 °C) or Ethylene glycol (EG, T_flash-point = 116 °C). Three Silane (Head group) based monomers; with three different tail groups (e.g. amine, aniline and methacrylate) were investigated; The elevated temperature deposition process allowed shorter deposition times (less than 15 min), compared to previous publications. Additionally, the high flash point solvents reduce the risk of spontaneous explosion or ignition. All three monomers yielded satisfactory barrier against copper transport, being tested for more than 10 h at temperature higher than 400 °C, on all substrates. The need for a quick turn-around and a simple way to determine the barrier presence, its thickness and its coverage, lead to explore the application of Electrochemical Impedance Spectroscopy (EIS). We demonstrate the capability of that method estimating thickness and coverage of such ultra-thin barriers deposited on relatively thick (~200 nm) Low-K dielectric materials. It was found that EIS below 10 Hz at negative wafer bias vs. the electrolyte reference, the impedance real part was affected by the ultra-thin layer on thick dielectric materials allowing to define an Effective Electrical Coverage (EEC) of the films on Low-K dielectric similar to what has already been defined on bare silicon. The EEC is a figure of merit and its relation to the actual surface coverage, and barrier properties, is briefly discussed.