C-Flash: An ultra-low power single poly logic NVM

Y. Roizin*, E. Aloni, A. Birman, V. Dayan, A. Fenigstein, D. Nahmad, E. Pikhay, D. Zfira

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An ultra-low power logic NVM has currents <10nA/cell in all operating regimes, high programming/erase speeds, excellent endurance / retention and allows strong Vdd fluctuations. The memory uses CMOS inverter read-out principle (C-Flash) and F-N injection for programming and erase with voltages below +5V. The memory is intended for RFID and advanced mobile applications requiring small/middle sized embedded memory modules.

Original languageEnglish
Title of host publication2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD
Pages90-92
Number of pages3
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, NVSMW/ICMTD - Opio, France
Duration: 18 May 200822 May 2008

Publication series

Name2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD

Conference

Conference2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, NVSMW/ICMTD
Country/TerritoryFrance
CityOpio
Period18/05/0822/05/08

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