Buffered deflection routing for networks-on-chip

Gadi Oxman*, Shlomo Weiss, Yitzhak Birk

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Bufferless deflection routing works surprisingly well when the network traffic is light or medium, and can outperform a virtual channel router with a small number of buffers, but when the network is working closer to saturation, classic buffered virtual channel routers can sustain higher data rates, provided enough buffers are used. In this paper, we investigate extending bufferless deflection routing using the addition of router buffers. We propose two buffered deflection routing flow control algorithms that naturally extend bufferless deflection routing and still keep its attractive characteristics. We evaluate the proposed algorithms using a cycle accurate NoC simulator, and compare the results to bufferless deflection routing and virtual channel router with the same number of buffers. Our results show that buffered deflection routing offers substantial throughput gains while allowing a very efficient use of each added buffer, and can therefore be attractive for on-chip networks under heavy load.

Original languageEnglish
Title of host publicationProceedings of the 2012 Interconnection Network Architecture
Subtitle of host publicationOn-Chip, Multi-Chip Workshop, INA-OCMC'12
Pages9-12
Number of pages4
DOIs
StatePublished - 2012
Event2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, INA-OCMC'12 - Paris, France
Duration: 25 Jan 201225 Jan 2012

Publication series

NameACM International Conference Proceeding Series

Conference

Conference2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, INA-OCMC'12
Country/TerritoryFrance
CityParis
Period25/01/1225/01/12

Keywords

  • buffering
  • deflection routing
  • flow control
  • networks-on-chip
  • routing architectures

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