TY - GEN
T1 - Buffered deflection routing for networks-on-chip
AU - Oxman, Gadi
AU - Weiss, Shlomo
AU - Birk, Yitzhak
PY - 2012
Y1 - 2012
N2 - Bufferless deflection routing works surprisingly well when the network traffic is light or medium, and can outperform a virtual channel router with a small number of buffers, but when the network is working closer to saturation, classic buffered virtual channel routers can sustain higher data rates, provided enough buffers are used. In this paper, we investigate extending bufferless deflection routing using the addition of router buffers. We propose two buffered deflection routing flow control algorithms that naturally extend bufferless deflection routing and still keep its attractive characteristics. We evaluate the proposed algorithms using a cycle accurate NoC simulator, and compare the results to bufferless deflection routing and virtual channel router with the same number of buffers. Our results show that buffered deflection routing offers substantial throughput gains while allowing a very efficient use of each added buffer, and can therefore be attractive for on-chip networks under heavy load.
AB - Bufferless deflection routing works surprisingly well when the network traffic is light or medium, and can outperform a virtual channel router with a small number of buffers, but when the network is working closer to saturation, classic buffered virtual channel routers can sustain higher data rates, provided enough buffers are used. In this paper, we investigate extending bufferless deflection routing using the addition of router buffers. We propose two buffered deflection routing flow control algorithms that naturally extend bufferless deflection routing and still keep its attractive characteristics. We evaluate the proposed algorithms using a cycle accurate NoC simulator, and compare the results to bufferless deflection routing and virtual channel router with the same number of buffers. Our results show that buffered deflection routing offers substantial throughput gains while allowing a very efficient use of each added buffer, and can therefore be attractive for on-chip networks under heavy load.
KW - buffering
KW - deflection routing
KW - flow control
KW - networks-on-chip
KW - routing architectures
UR - http://www.scopus.com/inward/record.url?scp=84856861026&partnerID=8YFLogxK
U2 - 10.1145/2107763.2107766
DO - 10.1145/2107763.2107766
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AN - SCOPUS:84856861026
SN - 9781450310109
T3 - ACM International Conference Proceeding Series
SP - 9
EP - 12
BT - Proceedings of the 2012 Interconnection Network Architecture
T2 - 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, INA-OCMC'12
Y2 - 25 January 2012 through 25 January 2012
ER -