# Black box polynomial identity testing of generalized depth-3 arithmetic circuits with bounded top fan-in

Zohar S. Karnin, Amir Shpilka

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

## Abstract

In this paper we consider the problem of determining whether an unknown arithmetic circuit, for which we have oracle access, computes the identically zero polynomial. This problem is known as the black-box polynomial identity testing (PIT) problem. Our focus is on polynomials that can be written in the form f(x̄) = σhi(x ̄) · 9i{x̄), where each hi is a polynomial that depends on at most & linear functions, and each gi is a product of linear functions {when h i = 1, for each i, then we get the class of depth-3 circuits with k multiplication gates, also known as σIIσ(k) circuits, but the general case is much richer). When maxi(deg(hi · gi)) = d we say that f is computable by a σIIσ(k, d, ρ) circuit. We obtain the following results. 1. A deterministic black-box identity testing algorithm for σIIσ(k, d, ρ) circuits that runs in quasi-polynomial time (for ρ = polylog(n + d)). 2. A deterministic black-box identity testing algorithm for read-k σIIσ circuits (depth-3 circuits where each variable appears at most k times) that runs in time n2o(k2) This gives a polynomial time algorithm for k = O(1). These are the first sub-exponential black-box PIT algorithms for circuits of depth higher than 2. Our results can also be stated in terms of test sets for the underlying circuit model. A test set is a set of points s.t. if two circuits get the same values on every point of the set then they compute the same polynomial. Thus, our first result gives an explicit test set, of quasi-polynomial size, for σIIσ(k, d, ρ) circuits (for ρ = polylog(n + d)). Our second result gives an explicit polynomial size test set for read-k depth-3 circuits. The proof technique involves a construction of a family of affine subspaces that have a rank-preserving property that is inspired by the construction of linear seeded extractors for affine sources of Gabizon and Raz [9], and a generalization of a theorem of [8] regarding the structure of identically zero depth-3 circuits with bounded top fan-in.

Original language English Proceedings - 23rd Annual IEEE Conference on Computational Complexity, CCC 2008 280-291 12 https://doi.org/10.1109/CCC.2008.15 Published - 2008 Yes 23rd Annual IEEE Conference on Computational Complexity, CCC 2008 - College Park, MD, United StatesDuration: 23 Jun 2008 → 26 Jun 2008

### Publication series

Name Proceedings of the Annual IEEE Conference on Computational Complexity 1093-0159

### Conference

Conference 23rd Annual IEEE Conference on Computational Complexity, CCC 2008 United States College Park, MD 23/06/08 → 26/06/08

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