Barrier layers for CU ULSI metallization

Barrier layers are integral parts of many metal interconnect systems. In this paper we review the current status of barrier layers for copper metallization for ultra-large-scale-integration (ULSI) technology for integrated circuits (ICs) manufacturing. The role of barrier layers is reviewed and the criteria that determine the process window, i.e. the optimum barrier thickness and the deposition processes, for their manufacturing are discussed. Various deposition methods are presented: physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), electroless deposition (ELD), and atomic layer CVD (ALCVD) for barrier layers implementation. The barrier integration methods and the interaction between the barrier and the copper metallization are presented and discussed. Finally, the common inspection and metrology for barrier layer are critically reviewed.