Abstract
This paper presents a CAD tool which incorporates several approaches to the design of reliable checkers for control units (devices which control the operation of other devices). Part of the approaches are traditional, part original. The main contribution of this paper is the automation of the design of checkers for lookup-table (LUT) based FPGA architecture, with aspiration to minimum hardware.
| Original language | English |
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| Pages | 122-125 |
| Number of pages | 4 |
| State | Published - 2004 |
| Externally published | Yes |
| Event | 2004 23rd IEEE Convention of Electrical and Electronics Engineers in Israel, Proceedings - Tel-Aviv, Israel Duration: 6 Sep 2004 → 7 Sep 2004 |
Conference
| Conference | 2004 23rd IEEE Convention of Electrical and Electronics Engineers in Israel, Proceedings |
|---|---|
| Country/Territory | Israel |
| City | Tel-Aviv |
| Period | 6/09/04 → 7/09/04 |