Arbitrary error detection in combinational circuits by using partitioning

Osnat Keren*, Ilya Levin, Vladimir Ostrovsky, Beni Abramov

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuits. It does not require any redundant coding variables; instead, it utilizes a sub-set of input variables. These variables are transferred directly into a checker providing the arbitrary error detection. The paper develops and studies a method for selecting an optimized sub-set of such variables. Benchmark results show efficiency of the proposed approach.

Original languageEnglish
Article number4641192
Pages (from-to)361-369
Number of pages9
JournalProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOIs
StatePublished - 2008
Event23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States
Duration: 1 Oct 20083 Oct 2008

Fingerprint

Dive into the research topics of 'Arbitrary error detection in combinational circuits by using partitioning'. Together they form a unique fingerprint.

Cite this