The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuits. It does not require any redundant coding variables; instead, it utilizes a sub-set of input variables. These variables are transferred directly into a checker providing the arbitrary error detection. The paper develops and studies a method for selecting an optimized sub-set of such variables. Benchmark results show efficiency of the proposed approach.
|Number of pages||9|
|Journal||Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems|
|State||Published - 2008|
|Event||23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States|
Duration: 1 Oct 2008 → 3 Oct 2008