A study is presented of a storage strategy for vector processors that has the following properties: (1) it is aperiodic, (2) it tends to distribute references more uniformly over the memory banks, (3) the implementaion of the addressing hardware is straightforward, and (4) the delay added to the memory path is minimal. The first two properties help in reducing the frequency of bank conflicts. A comparison with the simple storage strategy used in most vector processors demonstrates a significant increase in the efficiency of the parallel memory system. This increase is mainly attributable to a more even distribution of references over the memory banks. The difference between the two storage strategies is more apparent when the bank busy time is longer. The simulations also show that the higher performance of the prposed storage scheme depends on the presence of queues in the memory system. For the parameters studied, no performance improvement has been observed for queues longer than four stages.
|Number of pages||7|
|Journal||Conference Proceedings - Annual Symposium on Computer Architecture|
|State||Published - 1989|
|Event||16th Annual International Symposium on Computer Architecture - Jerusalem, Israel|
Duration: 28 May 1989 → 1 Jun 1989