An SRAM based on the MSET device

Assaf Peled; Xuan Hu; Ofer Amrani; Joseph S. Friedman; Yossi Rosenwaks

doi:10.1109/TED.2019.2892319

An SRAM based on the MSET device

Assaf Peled^*, Xuan Hu, Ofer Amrani, Joseph S. Friedman, Yossi Rosenwaks

^*Corresponding author for this work

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

From its conceptual inception in 2015, the combined capabilities of the multiple-state electrostatically formed nanowire transistor (MSET) have given way to a unique set of logic structures-in the example of NAND and NOR gates-which utilize fewer transistors as compared to conventional technologies. In this paper, we expand the recently published framework of MSET logic functions and present a static random access memory (SRAM) memory structure that consists entirely of MSET devices. Using TCAD simulations, we demonstrate the MSET-SRAM functionality in several phases of operation, while analyzing its performance in terms of speed, stability, and power consumption.

Original language	English
Article number	8626485
Pages (from-to)	1262-1267
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	3
DOIs	https://doi.org/10.1109/TED.2019.2892319
State	Published - Mar 2019

Keywords

Device simulations
Multigate transistors
Multiple-state electrostatically formed nanowire transistor (MSET) transistor
Static random access memory (SRAM)

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10.1109/TED.2019.2892319

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@article{b6bd3f4aca2640bdb3b815a39db0bd7e,

title = "An SRAM based on the MSET device",

abstract = "From its conceptual inception in 2015, the combined capabilities of the multiple-state electrostatically formed nanowire transistor (MSET) have given way to a unique set of logic structures-in the example of NAND and NOR gates-which utilize fewer transistors as compared to conventional technologies. In this paper, we expand the recently published framework of MSET logic functions and present a static random access memory (SRAM) memory structure that consists entirely of MSET devices. Using TCAD simulations, we demonstrate the MSET-SRAM functionality in several phases of operation, while analyzing its performance in terms of speed, stability, and power consumption.",

keywords = "Device simulations, Multigate transistors, Multiple-state electrostatically formed nanowire transistor (MSET) transistor, Static random access memory (SRAM)",

author = "Assaf Peled and Xuan Hu and Ofer Amrani and Friedman, {Joseph S.} and Yossi Rosenwaks",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.",

year = "2019",

month = mar,

doi = "10.1109/TED.2019.2892319",

language = "אנגלית",

volume = "66",

pages = "1262--1267",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - An SRAM based on the MSET device

AU - Peled, Assaf

AU - Hu, Xuan

AU - Amrani, Ofer

AU - Friedman, Joseph S.

AU - Rosenwaks, Yossi

PY - 2019/3

Y1 - 2019/3

N2 - From its conceptual inception in 2015, the combined capabilities of the multiple-state electrostatically formed nanowire transistor (MSET) have given way to a unique set of logic structures-in the example of NAND and NOR gates-which utilize fewer transistors as compared to conventional technologies. In this paper, we expand the recently published framework of MSET logic functions and present a static random access memory (SRAM) memory structure that consists entirely of MSET devices. Using TCAD simulations, we demonstrate the MSET-SRAM functionality in several phases of operation, while analyzing its performance in terms of speed, stability, and power consumption.

AB - From its conceptual inception in 2015, the combined capabilities of the multiple-state electrostatically formed nanowire transistor (MSET) have given way to a unique set of logic structures-in the example of NAND and NOR gates-which utilize fewer transistors as compared to conventional technologies. In this paper, we expand the recently published framework of MSET logic functions and present a static random access memory (SRAM) memory structure that consists entirely of MSET devices. Using TCAD simulations, we demonstrate the MSET-SRAM functionality in several phases of operation, while analyzing its performance in terms of speed, stability, and power consumption.

KW - Device simulations

KW - Multigate transistors

KW - Multiple-state electrostatically formed nanowire transistor (MSET) transistor

KW - Static random access memory (SRAM)

UR - http://www.scopus.com/inward/record.url?scp=85062284421&partnerID=8YFLogxK

U2 - 10.1109/TED.2019.2892319

DO - 10.1109/TED.2019.2892319

M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???

AN - SCOPUS:85062284421

SN - 0018-9383

VL - 66

SP - 1262

EP - 1267

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

M1 - 8626485

ER -

An SRAM based on the MSET device

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