An SRAM based on the MSET device

Assaf Peled*, Xuan Hu, Ofer Amrani, Joseph S. Friedman, Yossi Rosenwaks

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


From its conceptual inception in 2015, the combined capabilities of the multiple-state electrostatically formed nanowire transistor (MSET) have given way to a unique set of logic structures-in the example of NAND and NOR gates-which utilize fewer transistors as compared to conventional technologies. In this paper, we expand the recently published framework of MSET logic functions and present a static random access memory (SRAM) memory structure that consists entirely of MSET devices. Using TCAD simulations, we demonstrate the MSET-SRAM functionality in several phases of operation, while analyzing its performance in terms of speed, stability, and power consumption.

Original languageEnglish
Article number8626485
Pages (from-to)1262-1267
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number3
StatePublished - Mar 2019


  • Device simulations
  • Multigate transistors
  • Multiple-state electrostatically formed nanowire transistor (MSET) transistor
  • Static random access memory (SRAM)


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