An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation

Gadi Oxman, Shlomo Weiss

Research output: Contribution to journalArticlepeer-review

Abstract

We present deflection routing network on chip simulator (DNOC), a network-on-chip simulator. DNOC is primarily a deflection routing simulator, it simulates custom network topologies with detailed deflection router models, and a basic virtual channel router. DNOC can generate various statistics, such as network latency and power. We evaluate the simulator in three typical use cases. In stand-alone simulation, synthetic traffic generators are used to offer load to the network. In synchronous co-simulation, the simulator is integrated as a module within a larger system simulator with synchronization every simulated cycle. In the faster model-based co-simulation mode, a latency model is built, and retuned periodically at longer time intervals. We demonstrate co-simulation by running applications from the Rodinia and SPLASH-2 benchmark sets on mesh variants. DNOC is also able to run on multicore processors, speeding up the simulation of large networks.

Original languageEnglish
Article number7416189
Pages (from-to)1667-1680
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume35
Issue number10
DOIs
StatePublished - Oct 2016

Keywords

  • Modeling
  • Simulation
  • networks-on-chip (NoCs)
  • routing

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