An Inductorless, 0.5mA/15fJ, Small Footprint, SiGe BiCMOS Quasi-Current-Mode Logic Family for Highly Parallelized, 40GHz Clock SAR ADCs

P. Hermansen, E. Socher, D. Case, A. Cathelin, P. Chevalier, T. Nguyen, S. P. Voinigescu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An ultra-low-power MOS-HBT quasi-CML family based on active peaking and the minimum size (0.1×0.35) SiGe HBT is investigated. It features a novel SR-latch topology which is used to demonstrate the highest frequency multiphase clock generator with eight 6.25% duty cycle output signals at input clock frequencies between 3 and 42 GHz, and the highest sampling rate SAR ADC lane in any semiconductor technology. The layout footprint of the fabricated 8-phase clock generator takes up 105 × 50 while the area and power consumption of the SAR ADC are 200×40 and 70 mW, respectively. The 6-bit SAR ADC lane, whose performance is limited by SAR metastability due to loop delay, achieves 4.4 and 3.8-bits ENOB at 2.5 GS/s and 3 GS/s, respectively, with an SFDR larger than 31 dB over the entire Nyquist band. The total area of the ADC, including the 8-phase clock generator is 1.07mm × 0.985mm.

Original languageEnglish
Title of host publication2019 IEEE MTT-S International Microwave Symposium, IMS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages738-741
Number of pages4
ISBN (Electronic)9781728113098
DOIs
StatePublished - Jun 2019
Externally publishedYes
Event2019 IEEE MTT-S International Microwave Symposium, IMS 2019 - Boston, United States
Duration: 2 Jun 20197 Jun 2019

Publication series

NameIEEE MTT-S International Microwave Symposium Digest
Volume2019-June
ISSN (Print)0149-645X

Conference

Conference2019 IEEE MTT-S International Microwave Symposium, IMS 2019
Country/TerritoryUnited States
CityBoston
Period2/06/197/06/19

Keywords

  • CML
  • SAR ADC
  • SiGe BiCMOS
  • active inductor
  • phase generator

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