An ultra-low-power MOS-HBT quasi-CML family based on active peaking and the minimum size (0.1×0.35) SiGe HBT is investigated. It features a novel SR-latch topology which is used to demonstrate the highest frequency multiphase clock generator with eight 6.25% duty cycle output signals at input clock frequencies between 3 and 42 GHz, and the highest sampling rate SAR ADC lane in any semiconductor technology. The layout footprint of the fabricated 8-phase clock generator takes up 105 × 50 while the area and power consumption of the SAR ADC are 200×40 and 70 mW, respectively. The 6-bit SAR ADC lane, whose performance is limited by SAR metastability due to loop delay, achieves 4.4 and 3.8-bits ENOB at 2.5 GS/s and 3 GS/s, respectively, with an SFDR larger than 31 dB over the entire Nyquist band. The total area of the ADC, including the 8-phase clock generator is 1.07mm × 0.985mm.