@inproceedings{8b03630fa7554abaa84e40dff8857a43,
title = "An Inductorless, 0.5mA/15fJ, Small Footprint, SiGe BiCMOS Quasi-Current-Mode Logic Family for Highly Parallelized, 40GHz Clock SAR ADCs",
abstract = "An ultra-low-power MOS-HBT quasi-CML family based on active peaking and the minimum size (0.1×0.35) SiGe HBT is investigated. It features a novel SR-latch topology which is used to demonstrate the highest frequency multiphase clock generator with eight 6.25% duty cycle output signals at input clock frequencies between 3 and 42 GHz, and the highest sampling rate SAR ADC lane in any semiconductor technology. The layout footprint of the fabricated 8-phase clock generator takes up 105 × 50 while the area and power consumption of the SAR ADC are 200×40 and 70 mW, respectively. The 6-bit SAR ADC lane, whose performance is limited by SAR metastability due to loop delay, achieves 4.4 and 3.8-bits ENOB at 2.5 GS/s and 3 GS/s, respectively, with an SFDR larger than 31 dB over the entire Nyquist band. The total area of the ADC, including the 8-phase clock generator is 1.07mm × 0.985mm.",
keywords = "CML, SAR ADC, SiGe BiCMOS, active inductor, phase generator",
author = "P. Hermansen and E. Socher and D. Case and A. Cathelin and P. Chevalier and T. Nguyen and Voinigescu, {S. P.}",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE MTT-S International Microwave Symposium, IMS 2019 ; Conference date: 02-06-2019 Through 07-06-2019",
year = "2019",
month = jun,
doi = "10.1109/mwsym.2019.8701086",
language = "אנגלית",
series = "IEEE MTT-S International Microwave Symposium Digest",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "738--741",
booktitle = "2019 IEEE MTT-S International Microwave Symposium, IMS 2019",
address = "ארצות הברית",
}