A dual band F-band packaged transceiver at 95GHz and 130GHz in 65nm CMOS technology is presented. The transceiver architecture is based on a bi-directional operation with a maximum data rate of up to 12Gbps per band. Maximum output power on-chip of -0.5dBm and -1.5dBm were achieved in the low band (95GHz) and high band (130GHz) respectively and 12+12Gbps modulated signals are measured off-chip in the transmit mode. In the receive mode a BER<10-12 was achieved for the low band with data rates up to 12Gbps limited by the measurement equipment. The packaged transceiver demonstrates 10+10Gbps wireline bi-directional half-duplex communication with 41mW power consumption and 10+8Gbps full-duplex communication with 37.5mW power consumption, thus achieving 2pJ/bit of energy efficiency in the whole transceiver. The chip occupies an overall area of only 0.44mm2.