An F-band 20.6Gbp/s QPSK transmitter in 65nm CMOS

Eli Bloch, Eran Socher

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We hereby report the design and measurements of a 101-118 GHz 65 nm CMOS transmitter. The transmitter architecture is based on a two-step upconversion using a single 80 GHz LO with the quadrature phases generated by injection locked frequency dividers. Both BPSK and QPSK modulations with a maximum datarate of 20.6 Gbps are supported. A measured output power of -5 dBm at 115 GHz and an error-vector magnitude of 17.5% for 30 dB conversion-loss downconversion link are obtained. The chip core area is 0.21 mm2 and a DC power consumption of 280 mW.

Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages299-302
Number of pages4
ISBN (Print)9781479938629
DOIs
StatePublished - 2014
Event2014 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2014 - Tampa Bay, FL, United States
Duration: 1 Jun 20143 Jun 2014

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2014 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2014
Country/TerritoryUnited States
CityTampa Bay, FL
Period1/06/143/06/14

Keywords

  • CMOS integrated circuits
  • Injection-locked oscillators
  • Millimeter wave integrated circuits
  • Mixers
  • Phase modulation
  • Transmitters
  • Wireless Communication

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