A Zero Bias J-Band Antenna-Coupled Detector in 65-nm CMOS

Edoh Shaulov, Samuel Jameson, Eran Socher

Research output: Contribution to journalArticlepeer-review

Abstract

An improved topology for sub-THz radiation detection realized in 65 nm CMOS, including an on-chip antenna and using zero biasing is presented in this article. The topology is based on a differential Colpitts topology working in reverse-mode and leverages the nonlinearity with respect to vDS in subthreshold operation to rectify. The use of tuned inductors at the gates and sources of the transistor core create degenerative resonance feedback, which further enhances the responsivity while working with zero bias eliminates 1/f noise to improve the NEP. Measurements demonstrated a voltage responsivity as high as 2 kV/W with a 3 dB RF BW of at least 50 GHz centered at 315 GHz and a record NEP of down to 3.5 pW/√Hz, verified both at zero-IF and using chopping from 0.5 Hz up to 2 kHz. The chip occupies an area of 0.165 mm2 including pads.

Original languageEnglish
Article number9258918
Pages (from-to)62-69
Number of pages8
JournalIEEE Transactions on Terahertz Science and Technology
Volume11
Issue number1
DOIs
StatePublished - Jan 2021

Keywords

  • 65 nm
  • CMOS
  • J-band
  • NEP
  • THz
  • antenna
  • chip scale dielectric resonator antenna (CSDRA)
  • detector
  • mm-Wave
  • responsivity

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