TY - JOUR

T1 - A Unified Approach to Closed-Loop Time Delay Estimation Systems

AU - Messer, Hagit

PY - 1988/6

Y1 - 1988/6

N2 - Recently, closed-loop delay estimation systems (CLDES) have gained considerable interest. In this paper, two generalized configurations for a closed-loop delay estimation system are discussed. The indirect correlation (IC) configuration is compared to the conventional CLDES–the direct correlation (DC) configuration. It is shown that the baseband equivalents of the two configurations differ only by the input noise. However, the noise power in the IC configuration is far less than that of the DC configuration. Using the known procedure for calculation of the variance of the time delay estimator, we show that the two configurations result in the same variance. However, this procedure is known to be incorrect since, for the direct correlation configuration (which is known to have an intrinsic noise that persists even when the input signals are ideal), the variance is nonzero for zero input SNR. Thus, we suggest another procedure for variance calculation that overcomes this problem, and it is shown, using our expression, that the variance of the time delay estimator is smaller for the IC configuration, provided the input SNR is not less that 0 dB.

AB - Recently, closed-loop delay estimation systems (CLDES) have gained considerable interest. In this paper, two generalized configurations for a closed-loop delay estimation system are discussed. The indirect correlation (IC) configuration is compared to the conventional CLDES–the direct correlation (DC) configuration. It is shown that the baseband equivalents of the two configurations differ only by the input noise. However, the noise power in the IC configuration is far less than that of the DC configuration. Using the known procedure for calculation of the variance of the time delay estimator, we show that the two configurations result in the same variance. However, this procedure is known to be incorrect since, for the direct correlation configuration (which is known to have an intrinsic noise that persists even when the input signals are ideal), the variance is nonzero for zero input SNR. Thus, we suggest another procedure for variance calculation that overcomes this problem, and it is shown, using our expression, that the variance of the time delay estimator is smaller for the IC configuration, provided the input SNR is not less that 0 dB.

UR - http://www.scopus.com/inward/record.url?scp=0024029310&partnerID=8YFLogxK

U2 - 10.1109/29.1596

DO - 10.1109/29.1596

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AN - SCOPUS:0024029310

SN - 1053-587X

VL - 36

SP - 854

EP - 861

JO - IEEE Transactions on Signal Processing

JF - IEEE Transactions on Signal Processing

IS - 6

ER -