A study of scalar compilation techniques for pipelined supercomputers

Shlomo Weiss, James E. Smith

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


This paper studies two compilation techniques for enhancing scalar performance in high-speed scientific processors: software pipelining and loop unrolling. We study the impact of the architecture (size of the register file) and of the hardware (size of instruction buffer) on the efficiency of loop unrolling. We also develop a methodology for classifying software pipelining techniques. For loop unrolling, a straightforward scheduling algorithm is shown to produce near-optimal results when not inhibited by recurrences or memory hazards. Software pipelining requires less hardware but also achieves less speedup. Finally, we show that the performance produced with a modified CRAY-1S scalar architecture and a code scheduler utilizing loop unrolling is comparable to the performance achieved by the CRAY-1S with a vector unit and the CFT vectorizing compiler.

Original languageEnglish
Pages (from-to)105-109
Number of pages5
JournalACM SIGPLAN Notices
Issue number10
StatePublished - 1 Oct 1987
Externally publishedYes


FundersFunder number
National Science FoundationECS-8207277


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