With the significant increase of wireless standards in recent years, reconfigurable programmable architectures have started to attract more attention and interest. One of the solutions that has gained more industry-popularity is the Application Specific Instruction-Set (ASIP) Processor, which provides an innovative approach for obtaining flexibility with relatively small increases in area and power. In this article we will present the development of an optimized ASIP that is tailored to the needs of detecting packets based on the 802.11 standard, and uses a retargetable compilation flow. We will present several optimizations that can be used to optimize both the algorithm and the processor model. These enhancements increase the performance by a factor of 20 and decrease significantly the power consumption relative to a 16bit general purpose processor model. While the proposed configurable ASIP was applied to multiple packet detection standards based on OFDM or DSSS modulations such as 802.11a/g/n and 802.11b/1997 respectively, it was verified on an ODFM 802.11a/g/n system. Most of our analysis focuses on OFDM systems, however, it also applies to DSSS systems. In addition, we present a comparison between the proposed ASIP and a dedicated hardware solution over ASIC in terms of performance power and area.