TY - JOUR
T1 - A real-time systolic integer multiplier
AU - Even, Guy
N1 - Funding Information:
However, the design of systolic arrays is complicated and the correctness of these circuits is difficult to understand. Retiming is a design methodology which was proposed by Leiserson and Saxe \[3\] for simplifying and improving the design of systolic arrays. Retiming has been a very successful technique in improving and simplifying previous designs. Leiserson and Saxe \[3\]d escribed a simple circuit which recognizes palindromes; it is much easier to understand, compared with previous treatments (such as Cole's \[4\] and Sieferas' \[5\]). Even and Litman \[6\] provided the first proof of Atrubin's multiplier \[7\] 29 years after it was invented. Our paper continues this line of * E-mail: [email protected]. 1This work was supported by the Miriam and Aaron Gutwirth Memorial Fellowship while the author was a D.Sc. student in the Computer-Science Department, Technion, Israel. An earlier version of this paper appeared in \[1,2\].
PY - 1997/8
Y1 - 1997/8
N2 - We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a non-pipelined multiplier. Our non-pipelined multiplier requires roughly half the hardware (number of full-adders) as compared to Atrubin's multiplier, which is the best real-time systolic multiplier known to-date. Our starting point is a serial/parallel multiplier which is not systolic, has a large number of primary inputs and does not support pipelining. We modify this design step by step using systematic methodologies until our design is obtained. The methodologies used in the design are: broadcast elimination, replacing parallel inputs with a broadcast mechanism and adding a simplified version of the circuit in order to enable pipelining. Applying these methodologies yields an improved circuit the correctness of which is easily understood.
AB - We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a non-pipelined multiplier. Our non-pipelined multiplier requires roughly half the hardware (number of full-adders) as compared to Atrubin's multiplier, which is the best real-time systolic multiplier known to-date. Our starting point is a serial/parallel multiplier which is not systolic, has a large number of primary inputs and does not support pipelining. We modify this design step by step using systematic methodologies until our design is obtained. The methodologies used in the design are: broadcast elimination, replacing parallel inputs with a broadcast mechanism and adding a simplified version of the circuit in order to enable pipelining. Applying these methodologies yields an improved circuit the correctness of which is easily understood.
UR - http://www.scopus.com/inward/record.url?scp=0031199246&partnerID=8YFLogxK
U2 - 10.1016/S0167-9260(97)00003-5
DO - 10.1016/S0167-9260(97)00003-5
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AN - SCOPUS:0031199246
SN - 0167-9260
VL - 22
SP - 23
EP - 38
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
IS - 1-2
ER -