A real-time systolic integer multiplier

Guy Even*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a non-pipelined multiplier. Our non-pipelined multiplier requires roughly half the hardware (number of full-adders) as compared to Atrubin's multiplier, which is the best real-time systolic multiplier known to-date. Our starting point is a serial/parallel multiplier which is not systolic, has a large number of primary inputs and does not support pipelining. We modify this design step by step using systematic methodologies until our design is obtained. The methodologies used in the design are: broadcast elimination, replacing parallel inputs with a broadcast mechanism and adding a simplified version of the circuit in order to enable pipelining. Applying these methodologies yields an improved circuit the correctness of which is easily understood.

Original languageEnglish
Pages (from-to)23-38
Number of pages16
JournalIntegration, the VLSI Journal
Issue number1-2
StatePublished - Aug 1997
Externally publishedYes


FundersFunder number
Miriam and Aaron Gutwirth Memorial Fellowship


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