A performance study of buffered pseudorandomly interleaved memories with multiple sections

In vector supercomputers, bank conflicts are often the dominant factor that determines the effective memory bandwidth and may lead to drastic reduction in the system performance. Primarily because of bank conflicts, users of the more recent CRAY-2 have difficulty in attaining performance comparable to that of the CRAY X-MP. Pseudorandom interleaving reduces the frequency of bank conflicts by "scrambling" the constant-stride reference string produced by the processor in vector mode. We develop a performance model for a memory system whose primary characteristics are, as in the CRAY-2, that the memory banks are organized into several sections and rejected memory requests are buffered in each processor. Unlike in the CRAY-2, we assume that the assignment of addresses to banks is done in a pseudorandom manner. This model is then used to report performance results as a function of several memory system parameters. We have obtained similar performance figures using Monte Carlo simulation.