A novel low power hybrid cache using GC-EDRAM cells

Junyi Zhou, Roger Kahn, Shlomo Weiss

Research output: Contribution to journalArticlepeer-review

Abstract

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU's chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM) [1–3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs.

Original languageEnglish
Pages (from-to)234-245
Number of pages12
JournalIntegration, the VLSI Journal
Volume81
DOIs
StatePublished - Nov 2021

Keywords

  • Cache
  • Embedded systems
  • Energy efficiency
  • Gain cell eDRAM

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