A Micro-architecture that supports the Fano–Elias encoding and a hardware accelerator for approximate membership queries

Keyphrases

• Microarchitecture 100%
• Dynamic Filter 100%
• Hardware Accelerator 100%
• Approximate Membership Query 100%
• Insertion-deletion 66%
• Logm 66%
• Hardware Design 66%
• Combinational Circuits 66%
• Filter Implementation 66%
• Latency 33%
• Expected number 33%
• Binary String 33%
• Clock Frequency 33%
• Cardinality 33%
• Number of Elements 33%
• Memory Bank 33%
• Bitstring 33%
• Gate Count 33%
• False Positive Error 33%
• Memory Access 33%
• Insertion Failure 33%
• Lite 33%
• 32-bit 33%
• Stable Throughput 33%
• Support to Operations 33%
• Combined Operation 33%
• Xilinx 33%
• Alveo 33%
• AXI4 33%
• Single Clock 33%
• Double Buffering 33%

Computer Science

• Microarchitecture 100%
• Clock Cycle 100%
• Hardware Accelerator 100%
• Hardware Design 66%
• Combinational Circuit 66%
• Input/Output 33%
• Cardinality 33%
• Critical Path 33%
• False Positive 33%
• Memory Access 33%
• Operation Support 33%
• Double Buffering 33%