A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits

Chua Chin Wang, Zong You Hou, Chih Lin Chen, Doron Shmilovitz

Research output: Contribution to journalArticlepeer-review

Abstract

This work presents a phase-locked loop (PLL)-based clock and data recovery (CDR) circuit with a lock detector loop to reduce the voltage ripple of voltage-controlled oscillator (VCO). A tunable charge pump is used in this work to adjust the charge current depending on the state of lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype is implemented using a typical 0.18-μ m CMOS process to justify the performance. The measurement results reveal that lock detector loop could reduce the voltage amplitude of Vctrl, which is the control of VCO. Notably, the voltage amplitude of Vctrl is reduced 75% from 1 V to 250 mV.

Original languageEnglish
Pages (from-to)1692-1703
Number of pages12
JournalCircuits, Systems, and Signal Processing
Volume37
Issue number4
DOIs
StatePublished - 1 Apr 2018

Keywords

  • CDR
  • Lock detector loop
  • Low power
  • PLL
  • Ripple reduction

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