A High Sensitivity CMOS Rectifier for 5G mm-Wave Energy Harvesting

This manuscript details the design and analysis of a CMOS rectifier in TSMC 65 nm for the 5G NR2 band and aims to overcome the challenge of achieving high rectified voltage while optimizing for PCE (power conversion efficiency). Using a frequency-scaled testbench, the transistor currents are investigated, providing key insights on the rectification mechanism that guide the design. The testbench is then used to determine the optimal number, N, of summing rectifiers to be used in a power splitting and voltage summing strategy that maximizes PCE for high target output voltage. In addition, a unit-cell rectifier design highlights how to target a specific output voltage while maintaining dc power matching for optimal PCE. Two rectifiers are presented: a unit-cell rectifier targeting-13 dBm and an N-scaled rectifier targeting-10 dBm. Both designs achieve a PCE of 15% at 27.5 GHz, while the former achieves 200 mV and the latter achieves 400 mV output voltage, for their respective target input powers. Finally, a survey of rectifiers operating around 30 GHz is presented where a x2 improvement over the current state-of-the-art is ascertained.