A dual mode IEEE multiplier

Guy Even, Silvia M. Mueller, Peter Michael Seidel

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review


We present an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the latency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fifteen logic levels. A single-precision multiplication can be followed immediately by another multiplication of either single or double-precision. A double-precision multiplication requires one stall cycle, namely, two cycles after issuing a double-precision multiplication, a new multiplication of either precision can be issued. Therefore, the throughput in single-precision is one multiplication per clock cycle, and the throughput in double-precision is one multiplication per two clock cycles. Hardware cost is reduced by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions.

Original languageEnglish
Title of host publicationComputer Arithmetic
Subtitle of host publicationVolume III
PublisherWorld Scientific Publishing Co.
Number of pages8
ISBN (Electronic)9789814651141
ISBN (Print)9789814651134
StatePublished - 1 Jan 2015
Externally publishedYes


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