TY - JOUR
T1 - A comparison of three rounding algorithms for IEEE floating-point multiplication
AU - Even, Guy
AU - Seidel, Peter Michael
N1 - Funding Information:
A preliminary version of this work appeared as “A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication” in the Proceedings of the 14th IEEE Symposium on Computer Arithmetic, pp. 225-232, Adelaide, Australia, 14-16 April 1999. Guy Even's work was supported in part by Intel Israel Ltd. under grants awarded in 1997 and 1998. Peter-Michael Seidel's work was supported by the DFG Graduiertenkolleg “Effizienz und Komplexität von Algorithmen und Rechenanlagen,” Uni-versität des Saarlandes.
PY - 2000/7
Y1 - 2000/7
N2 - A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of Yu and Zyner [26] and of Quach et al. [17]. For each rounding algorithm, a logical description and a block diagram is given, the correctness is proven, and the latency is analyzed. We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision format, the latency of the new rounding algorithm is 12 logic levels compared to 14 logic levels in the algorithm of Quach et al. and 16 logic levels in the algorithm of Yu and Zyner.
AB - A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of Yu and Zyner [26] and of Quach et al. [17]. For each rounding algorithm, a logical description and a block diagram is given, the correctness is proven, and the latency is analyzed. We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision format, the latency of the new rounding algorithm is 12 logic levels compared to 14 logic levels in the algorithm of Quach et al. and 16 logic levels in the algorithm of Yu and Zyner.
KW - Floating-point arithmetic
KW - Floating-point multiplication
KW - IEEE 754 Standard
KW - IEEE rounding
UR - http://www.scopus.com/inward/record.url?scp=0034215589&partnerID=8YFLogxK
U2 - 10.1109/12.863033
DO - 10.1109/12.863033
M3 - ???researchoutput.researchoutputtypes.contributiontojournal.systematicreview???
AN - SCOPUS:0034215589
SN - 0018-9340
VL - 49
SP - 638
EP - 650
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
IS - 7
ER -