A 5G NR2 Gate-Biased CMOS Rectifier with Enhanced PDR

This letter compares the impact of fixed gate bias and self-bias CMOS rectifier performance in terms of power dynamic range, power conversion efficiency (PCE), and rectifier output voltage (VOUT); where the benefits of fixed bias are readily observed. The performance degradation in self-bias is then attributed to high S11-power sensitivity caused by the feedback between VOUT and transistor bias. This feedback also inhibits DC power matching between the rectifier output impedance and the load, which further degrades self-bias performance in terms of VOUT. These assertions are validated through the simulation and characterization of a fabricated rectifier in TSMC 65 nm, targeting the 5G NR2 band between 26.5 GHz and 29.5 GHz. The rectifier achieves a record 20% efficiency at -10 dBm input power, and 6% at -20 dBm leveraging an optimal gate bias of 250 mV. A 5G NR2 signal is then applied to the rectifier where enhanced power dynamic range (PDR) for fixed bias is exemplified.