30-46 GHz 1.5dB IL Negative Gate Control SPDT with 24.5dBm IP1 in 130nm CMOS

Sumeet Londhe, Noam Bar-Helmer, Samuel Jameson, Eran Socher

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper a novel way of improving IP1 of SPDT switches is presented. IP1 of a SPDT generally degrades with power due to the leakage to the isolated port. Adding a negative control to the off state of the switch improves IP1 performance considerably while lowering the insertion loss. Compared to traditional series/shunt SPDT designs the negative gate control shunt SPDT provides wider bandwidth, lower insertion loss, higher isolation and higher IP1. The negative gate control SPDT outperforms traditional SPDTs and state of the art achieving an insertion loss of 1.5dB with wide band isolation (20-50GHz) better than 23dB and an IP1 of 24.5dBm in low-cost 130nm CMOS.

Original languageEnglish
Title of host publicationEuMIC 2021 - 2021 16th European Microwave Integrated Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages213-216
Number of pages4
ISBN (Electronic)9782874870644
DOIs
StatePublished - 2021
Event16th European Microwave Integrated Circuits Conference, EuMIC 2021 - London, United Kingdom
Duration: 3 Apr 20224 Apr 2022

Publication series

NameEuMIC 2021 - 2021 16th European Microwave Integrated Circuits Conference

Conference

Conference16th European Microwave Integrated Circuits Conference, EuMIC 2021
Country/TerritoryUnited Kingdom
CityLondon
Period3/04/224/04/22

Keywords

  • 5G
  • CMOS
  • IP1
  • SPDT
  • array
  • efficiency

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